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AT28C64(X)
Device Operation
READ: The AT28C64 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. Th e outputs are put in a high
impedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) ini-
tiates a byte write. The address location is latched on the
falling edge of WE (or CE); the new data is latched on the
rising edge. Internally, the device performs a self-clear
before write. Once a byte write has been started, it will
automatically time itself to completion. Once a program-
ming operation has been initiated and for the duration of
t WC , a read operation will effectively be a polling operation.
FAST BYTE WRITE: The AT28C64E offers a byte write
time of 200 μs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
READY/BUSY: Pin 1 is an open drain RDY/BUSY output
that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the
same RDY/BUSY line. The RDY/BUSY pin is not con-
nected for the AT28C64X.
DATA POLLING: The AT28C64 provides DATA Polling to
signal the completion of a write cycle. During a write cycle,
an attempted read of the data being written results in the
complement of that data for I/O 7 (the other outputs are
indeterminate). When the write cycle is finished, true data
appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) V CC sense –
if V CC is below 3.8V (typical) the write function is inhibited;
(b) V CC power on delay – once V CC has reached 3.8V the
device will automatically time out 5 ms (typical) before
allowing a byte write; and (c) write inhibit – holding any one
of OE low, CE high or WE high inhibits byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip is
cleared when a 10 msec low pulse is applied to WE.
D E V I C E I DE NT I FI C A TI O N : A n e x t r a 3 2 b y t e s o f
EEPROM memory are available to the user for device iden-
tification. By raising A9 to 12 ± 0.5V and using address
locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
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